The present disclosure relates to levelization of memory interfaces for communicating with multiple memory devices.
Memory controllers generate command and address signals to write data to memory devices and read data from memory devices. In order to synchronize timings at which the command and address signals are received by the memory devices and the timings at which the data is written to or read from the memory devices between the memory controller and the memory devices, a system clock signal is typically used. The memory devices have various state machines and logic circuitries for processing the command and address signals and writing or reading data to or from the memory cells and communicating data and such command and address signals with the memory controller. Such state machines and logic circuitries operate clocked according to the system clock signal.
In some memory devices, the clock signal used by the memory controller is recovered in the memory devices so that the memory controller and the memory devices may be synchronized in timing when writing data to the memory devices or reading data from the memory devices. In some other memory devices, the memory controller is designed to forward the system clock signal it uses to the memory devices so that the memory devices can be synchronized to the same system clock signal when writing or reading data and transmitting the read data to the memory controller.
Generally, memory controllers are designed to interface with multiple memory devices to control memory access and write data to the memory devices or read data from the memory devices. When the memory controller forwards the system clock signal to multiple memory devices, the system clock signal is typically not propagated with the same delay within the multiple memory devices, because process variations during the fabrication process of each of the memory device integrated circuits (ICs) cause the various electronic components in the memory devices to have different delay in propagating the system clock signal. Since the state machines and various logic circuitries in the memory devices operate synchronized with the clock signal, the multiple memory devices may not read data and transmit the read data to the memory controller synchronized at the same timing, causing skew in the read memory data on the multiple lanes for communicating with the multiple memory devices.
In high speed memory interfaces having multiple data lanes, each lane in the memory PHY serializes parallel data (8-bit data for example) from the memory core into serial bit streams (3.2 Gbps, for example) and sends the serial bit steams to the corresponding lane in the memory controller. Each lane in the memory controller PHY uses its parallel clock (400 MHz, for example) to deserialize the bit streams back into 8-bit parallel data and to send the 8-bit parallel data to the memory controller core. The phase of the parallel clock determines 8-bit boundaries of the bit streams—correct phase is necessary to frame the bit-streams into the original 8-bit data from the memory core. The phase of the parallel clock is also constrained by its relationship to the memory controller core parallel clock. Because the memory controller core parallel clock is common for all lanes and the phase of parallel clocks in the memory controller PHY vary from lane to lane depending on the timing of its bit streams, the lane-to-lane skew of the bit streams needs to be controlled. Thus, conventional techniques for deskewing data on the multiple interfaces have been developed. For small lane-to-lane skew, the skewed data can be re-synchronized at the memory controller simply by having a synchronization latch. On the other hand, in a high speed serial memory interface that operates at a high clock frequency, the lane-to-lane clock skew due to process variation in the memory devices may be large, for example, as large as 4 UIs (unit intervals) for a clock that runs at 2.15 GHz to support 4.3 Gbps data rate in a double-data-rate (DDR) signaling.